मालवीय राष्ट्रीय प्रौद्योगिकी संस्थान जयपुर (राष्ट्रीय महत्व का संस्थान)
Malaviya National Institute of Technology Jaipur (An Institute of National Importance)
Department of Electronics & Communication Engineering


Journal Publications


Conference Publications


Research Projects


PhD Research Supervised

  • Ph.D.(VLSI Design) from Delhi Technological University, Delhi(2018)
    M. Tech.(Nano Science and Technology) from Delhi Technological University, Delhi(2013)
    B .Tech.(Electronics and Communication Engineering) from Rajasthan Technical University, Kota(2010)
Research Interests

Analog & Digital VLSI Design, Microelectronics, Low power VLSI systems, Nanoelectronics Device Modeling and Simulation.

Brief Research Profile

Dr. Bharat Choudhary has received his Ph.D degree in Digital VLSI Design and M.Tech degree in Nano Science and Technology from Delhi Technological University, New Delhi, India. He has received his B.Tech degree in Electronics and Communication Engineering from Rajasthan Technical University, Kota. He has qualified Engineering Services Examination - 2012 and opted Indian Naval Armament Service (INAS). Before joining MNIT, Jaipur as an Assistant Professor, he has worked in various capacities at Integrated Headquarters of Ministry of Defence (Navy), New Delhi. He has worked as Deputy Director from Jan 19 to Feb 20 and as Assistant Director from Dec 15 to Dec 18. He was involved in the planning, inventory control and provisioning of Naval Armaments/Weapon Systems along with the implementation of IT security policies dedicated for Indian Navy. His research interest includes Analog and Digital VLSI Design, Microelectronics, Low Power VLSI Systems and Nanoelectronics Device Modeling and Simulation.

Professional Background
  • Assistant Professor at Malaviya National Institute of Technology Jaipur [21 February 2020 - Present].
    Deputy Director at Indian Naval Armament Service [31 December 2018 - 20 February 2020].
    Assistant Director at Indian Naval Armament Service [21 December 2015 - 30 December 2018].

  • Vandana Singh Rajawat, Ajay Kumar, Bharat Choudhary, "Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide" , Memories-Materials, Devices, Circuits and Systems (Elsevier) Volume :5 (2023) / 1-9 / 2023 DOI: https://doi.org/10.1016/j.memori.2023.100079
  • 2021
  • Rahul, Bharat Choudhary, "An Advanced Genetic Algorithm with Improved Support Vector Machine for Multi-Class Classification of Real Power Quality Events" , Electric Power Systems Research (ELSEVIER) Volume :191 / 1-11 / 2021
  • 2017
  • Bharat Choudhary, Neeta Pandey, Kirti Gupta and Ankit Mittal , "New Sleep Based PFSCL Tri-State Inverter/Buffer Topologies" , Journal of Circuits, Systems and Computers (World Scientific) Volume :26 / 1-15 / 2017
  • 2016
  • Neeta Pandey, Kirti Gupta, Garima Bhatia and Bharat Choudhary, "MOS Current Mode Logic Exclusive-OR Gate Using Multi-threshold Triple-tail Cells" , Microelectronics Journal (Elsevier) Volume :57 / 13-20 / 2016
  • Bharat Choudhary, Neeta Pandey, Kirti Gupta and Ankit Mittal, "Bus Implementation Using New Low Power PFSCL Tristate Buffers" , Active and Passive Electronic Components Journal (Hindwai) Volume :2016 / 1-8 / 2016
  • Bharat Choudhary, Neeta Pandey and Kirti Gupta, "New Proposal for MCML based Three Input Logic Implementation" , VLSI Design Journal (Hindwai) Volume :2016 / 1-10 / 2016
  • Bharat Choudhary, Neeta Pandey, Damini Garg and Kirti Gupta, , "Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style" , Journal of Engineering (Hindwai) Volume :2016 / 1-10 / 2016
  • 2015
  • Bharat Choudhary and Neeta Pandey, "Improved tri-state buffer in MOS current mode logic and its application" , Analog Integrated Circuits and Signal Processing (Springer) Volume :84 / 333–340 / 2015
  • Bharat Choudhary, "New design of Exclusive-OR (EX-OR) gate by using low-power MCML tri-state buffer" , International Journal of Electronics, Electrical and Computational System (Academic Science) Volume :04 / 311-316 / 2015

  • Rahul, Bharat Choudhary, "Machine Learning and Deep Learning Based Hybrid Approach for Power Quality Disturbances Analysis" , 2023 International Conference on Computational Intelligence and Knowledge Economy: ICCIKE by :IEEE at Dubai, United Arab Emirates / 63-68 / 2023 ISBN: 979-8-3503-3827-0
  • Bharat Choudhary, "Implementation of Digital Applications Using Efficient CML Based Designs" , 2023 International Conference on Device Intelligence, Computing and Communication Technologies: DICCT by :IEEE at Dehradun, India / 125-130 / 2023 ISBN: 978-1-6654-7492-4
  • 2022
  • Vandana Singh Rajawat, Bharat Choudhary, Ajay Kumar, "High-K SOI GaN FinFET for High Power and High Frequency Applications" , 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter: EDKCON by :IEEE at Kolkata, India / 386-390 / 2022 ISBN: 978-1-6654-7206-7
  • 2018
  • Bharat Choudhary, Neeta Pandey and Kirti Gupta, "MCML Dynamic Register Design" , The International Symposium on Circuits and Systems (ISCAS) 2018 by :IEEE at Windsor, ON, Canada / 582-586 / 2018
  • 2015
  • Samiksha Agrawal, Neeta Pandey, Bharat Choudhary and Kirti Gupta, "Design of MCML ¬Based LFSR for Low Power and Mixed Signal Applications" , 12th IEEE India International Conference (INDICON 2015) by :IEEE at New Delhi / 1-6 / 2015

  • Senior Member of IEEE
  • Member of IEEE Electron Device Society
  • Executive Member Rajasthan Subsection of IEEE

  • Vandana Singh Rajawat on Design and Development of FinFET for High Performance Applications Year - 2021
  • Nidhish Tiwari on Design & Investigation of Gate Overlap Step Shape Double Gate (SSDG) TFET for Photosensing Applications Year - 2021
  • Ruchi Bhaskar on Optimization of Current Mode Logic Design Year - 2020

  • TANMAY KUMAR SAHU on Comprehensive IR drop Analysis and signoff methodology for hybrid 3DIC with back side power delivery Year - 2023-2024 (Ongoing)
  • YAMINI KEERTHANA on Physical Design using EDA tools Year - 2023-2024 (Ongoing)
  • 2022-2023
  • Jaishree on Optimization in MOS Current Mode Logic Circuit by using FGMOS Year - 2022-2023 (Completed)
  • Tanu Shree Gothwal on Development of Generic Custom FILL Parameterized Cell Year - 2022-2023 (Completed)
  • Ajay Kumar on Implementation & Analysis of Host memory Space addressed Data Transfer using User Space Driver for NVMe SSD controller Year - 2022-2023 (Completed)
  • Kriti Agarwal on Unified Verification Platform for Cross Domain Year - 2022-2023 (Completed)
  • Anvaya Srivastava on High Performance Bayer Image Compression Scheme Year - 2022-2023 (Completed)
  • 2021-2022
  • Himanshu Dayma on Optimization In Positive Feedback Source Coupled Logic (PFSCL) Circuit Design Using FGMOS Year - 2021-2022 (Completed)
  • Man Singh Prajapat on Optimization in MOS Current Mode Logic Circuit by using DTMOS Year - 2021-2022 (Completed)

  • Topic: Modification of MCML Designs for Low Power Applications Year - 2022-2023
    Agrima Gaur (Completed)
    Vivek Kumar (Completed)
    Ronak (Completed)
    Praveen Chauhan (Completed)
    Arunim Harsh (Completed)
  • Topic: Analysis of Leakage Current in PFSCL Design Using Dy-threshold Based MOSFET Year - 2021-2022
    Abhinav Singh Kushwah (Completed)
    Mukul Gupta (Completed)
    Ronak Nainiwal (Completed)
    Vishal Singh (Completed)
  • Topic: Modifications in MCML Design for Digital Applications Year - 2020-2021
    Paarth Bir (Completed)
    Naman Soni (Completed)
    Vishal Kothari (Completed)
    Aryan Rai (Completed)

Title Total Outlay
(In Lacs)
Year Funding Agency Role
Development of Silicon Proven IP Cores, Transceiver IC and System Prototype for mmWave Radar Sensing in Healthcare and Security Applications288.002023-2028MeitYCo-PI
Development of Artificial Intelligence based functional prototype for the diagnosis of Urinary Tract Infection10.002022-2023M/S Techjivaa Software Private Ltd.PI

  • Faculty Lab In-Charge, Advance Emerging Device Lab in MNIT Jaipur from - 04-02-2021 to Till Date
  • Hostel Warden in MNIT Jaipur from - 08-09-2020 to Till Date
  • Departmental Time Table Coordinator in MNIT Jaipur from - 10-08-2021 to 31-12-2022
  • Faculty Coordinator (Creative Arts & Cultural Society) in MNIT Jaipur from - 22-03-2021 to 09-10-2022
  • Deputy Director in Integrated Headquarters of Ministry of Defence (Navy) from - 31-12-2018 to 20-02-2020
  • Assistant Director in Integrated Headquarters of Ministry of Defence (Navy) from - 09-01-2017 to 30-12-2018
  • Assistant Manager in Naval Armament Depot from - 21-12-2015 to 08-01-2017

SNo. Type Title Event Place Schedule
1TalkVLSI DesignTEQIP-III Sponsored Workshop Organized by RIET Jaipur & RTU, Kota.OnlineFeb-2021
2TalkEmerging CMOS Technologies and Beyond: Trends and ChallengesWorkshopMNIT, JAIPURNov-2020

S.No. Category Name of Activity Organization Place Position Schedule
1NationalFive Day Online Workshop on "Emerging CMOS Technologies and Beyond: Trends and Challenges"MNIT, JaipurOnlineCoordinatorNov-2020
2NationalFDP on "Introduction to Low Power VLSI Design and Applications"NIT, WarangalOnlineResource PersonDec-2021
3NationalM.Tech. Project Viva-VoceDTU, DelhiOnlineExternal ExaminerSep-2021
4NationalM.Tech. Project Viva-VoceDTU, DelhiOnlineExternal ExaminerNov-2021
5InternationalInternational Conference on Cyber Technologies and Emerging Sciences (ICCTES 2021)Graphic Era Hill University, Bhimtal Campus, Uttarakhand, IndiaOnlineProgram Committee Member and ReviewerDec-2021
6InternationalIEEE International Symposium on Smart Electronic Systems [IEEE-iSES-2021] MNIT, JaipurMNIT, JaipurSession ChairDec-2021
7NationalFDP on "Low Power VLSI Design"NIT, WarangalOnlineResource PersonApr-2022